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ltc3780 1 3780fe typical application features applications description high ef ciency, synchronous, 4-switch buck-boost controller the ltc ? 3780 is a high performance buck-boost switch- ing regulator controller that operates from input voltages above, below or equal to the output voltage. the constant frequency current mode architecture allows a phase-lock- able frequency of up to 400khz. with a wide 4v to 30v (36v maximum) input and output range and seamless transfers between operating modes, the ltc3780 is ideal for automotive, telecom and battery-powered systems. the operating mode of the controller is determined through the fcb pin. for boost operation, the fcb mode pin can select among burst mode ? operation, discontinuous mode and forced continuous mode. during buck operation, the fcb mode pin can select among skip-cycle mode, discon- tinuous mode and forced continuous mode. burst mode operation and skip-cycle mode provide high ef? ciency operation at light loads while forced continuous mode and discontinuous mode operate at a constant frequency. fault protection is provided by an output overvoltage comparator and internal foldback current limiting. a power good output pin indicates when the output is within 7.5% of its designed set point. high ef? ciency buck-boost converter n single inductor architecture allows v in above, below or equal to v out n wide v in range: 4v to 36v operation n synchronous recti? cation: up to 98% ef? ciency n current mode control n 1% output voltage accuracy: 0.8v < v out < 30v n phase-lockable fixed frequency: 200khz to 400khz n power good output voltage monitor n internal ldo for mosfet supply n quad n-channel mosfet synchronous drive n v out disconnected from v in during shutdown n adjustable soft-start current ramping n foldback output current limiting n selectable low current modes n output overvoltage protection n available in 24-lead ssop and exposed pad (5mm 5mm) 32-lead qfn packages n automotive systems n telecom systems n dc power distribution systems n high power battery-operated devices n industrial control , lt, ltc, ltm and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6304066, 5929620, 5408150, 6580258, patent pending on current mode architecture and protection + v in tg2 0.1f 0.1f boost2 sw2 bg2 tg1 boost1 sw1 bg1 pllin run v osense i th ss sgnd fcb 0.010 4.7f a b d c 2200pf 1f cer 100f 16v cer 330f 16v on/off 0.1f 4.7h 20k pgood ltc3780 intv cc sense + sense C pgnd 7.5k 1% 3780 ta01 105k 1% 22f 50v cer v in 5v to 32v v out 12v 5a + v in (v) 0 efficiency (%) power loss (w) 90 95 100 15 25 3780 ta01b 85 80 510 20 30 35 75 70 8 9 10 7 6 5 4 3 2 1 0 ef? ciency and power loss v out = 12v, i load = 5a
ltc3780 2 3780fe absolute maximum ratings input supply voltage (v in ) ........................ C0.3v to 36v topside driver voltages (boost1, boost2) .................................. C0.3v to 42v switch voltage (sw1, sw2) ........................ C5v to 36v intv cc , extv cc , (boost C sw1), (boost2 C sw2), pgood .......................... C0.3v to 7v run, ss ....................................................... C0.3v to 6v pllin voltage .......................................... C0.3v to 5.5v pllfltr voltage ....................................... C0.3v to 2.7v fcb, stbymd voltages ........................ C0.3v to intv cc i th , v osense voltages .............................. C0.3v to 2.4v (note 1) peak output current <10s (tg1, tg2, bg1, bg2) .....3a intv cc peak output current ................................. 40ma operating junction temperature range (notes 5, 2, 7) ltc3780e ............................................. C40c to 85c ltc3780i............................................ C40c to 125c ltc3780mp ....................................... C55c to 125c junction temperature (note 2) ............................ 125c storage temperature range ................... C65c to 125c lead temperature (soldering, 10 sec) ssop only ........................................................ 300c 1 2 3 4 5 6 7 8 9 10 11 12 top view g package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 pgood ss sense + sense C i th v osense sgnd run fcb pllfltr pllin stbymd boost1 tg1 sw1 v in extv cc intv cc bg1 pgnd bg2 sw2 tg2 boost2 t jmax = 125c, ja = 130c/w 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 sense + sense C i th v osense sgnd run fcb pllftr sw1 v in extv cc intv cc bg1 pgnd bg2 sw2 nc ss pgood nc nc boost1 tg1 nc nc pllin stbymd nc nc boost2 tg2 nc t jmax = 125c, ja = 34c/w exposed pad (pin 33) is gnd, must be soldered to pcb pin configuration
ltc3780 3 3780fe electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v in = 15v unless otherwise noted. symbol parameter conditions min typ max units main control loop v osense feedback reference voltage i th = 1.2v, C40c t 85c (note 3) C55c t 125c l l 0.792 0.792 0.800 0.800 0.808 0.811 v v i vosense feedback pin input current (note 3) C5 C50 na v loadreg output voltage load regulation (note 3) ? i th = 1.2v to 0.7v ? i th = 1.2v to 1.8v l l 0.1 C0.1 0.5 C0.5 % % v ref(linereg) reference voltage line regulation v in = 4v to 30v, i th = 1.2v (note 3) 0.002 0.02 %/v g m(ea) error ampli? er transconductance i th = 1.2v, sink/source = 3a (note 3) 0.32 ms g m(gbw) error ampli? er gbw (note 8) 0.6 mhz i q input dc supply current normal standby shutdown supply current (note 4) v run = 0v, v stbymd > 2v v run = 0v, v stbymd = open 2400 1500 55 70 a a a v fcb forced continuous threshold 0.76 0.800 0.84 v i fcb forced continuous pin current v fcb = 0.85v C0.30 C0.18 C0.1 a v binhibit burst inhibit (constant frequency) threshold measured at fcb pin 5.3 5.5 v uvlo undervoltage reset v in falling l 3.8 4 v v ovl feedback overvoltage lockout measured at v osense pin 0.84 0.86 0.88 v i sense sense pins total source current v sense C = v sense + = 0v C380 a v stbymd(start) start-up threshold v stbymd rising 0.4 0.7 v v stbymd(ka) keep-alive power-on threshold v stbymd rising, v run = 0v 1.25 v order information lead free finish tape and reel part marking package description temperature range ltc3780eg#pbf ltc3780eg#trpbf ltc3780eg 24-lead plastic ssop C40c to 85c ltc3780ig#pbf ltc3780ig#trpbf ltc3780ig 24-lead plastic ssop C40c to 125c ltc3780euh#pbf ltc3780euh#trpbf 3780 32-lead (5mm 5mm) plastic qfn C40c to 85c ltc3780iuh#pbf ltc3780iuh#trpbf 3780i 32-lead (5mm 5mm) plastic qfn C40c to 125c lead based finish tape and reel part marking package description temperature range ltc3780eg ltc3780eg#tr ltc3780eg 24-lead plastic ssop C40c to 85c ltc3780ig ltc3780ig#tr ltc3780ig 24-lead plastic ssop C40c to 125c ltc3780mpg ltc3780mpg#tr ltc3780mpg 24-lead plastic ssop C55c to 125c ltc3780euh ltc3780euh#tr 3780 32-lead (5mm 5mm) plastic qfn C40c to 85c ltc3780iuh ltc3780iuh#tr 3780i 32-lead (5mm 5mm) plastic qfn C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc3780 4 3780fe electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v in = 15v unless otherwise noted. symbol parameter conditions min typ max units df max, boost maximum duty factor % switch c on 99 % df max, buck maximum duty factor % switch a on (in dropout) 99 % v run(on) run pin on threshold v run rising 1 1.5 2 v i ss soft-start charge current v run = 2v 0.5 1.2 a v sense(max) maximum current sense threshold boost: v osense = v ref C 50mv buck: v osense = v ref C 50mv l l C95 160 C110 185 C150 mv mv v sense(min,buck) minimum current sense threshold discontinuous mode C6 mv tg1, tg2 t r tg rise time c load = 3300pf (note 5) 50 ns tg1, tg2 t f tg fall time c load = 3300pf (note 5) 45 ns bg1, bg2 t r bg rise time c load = 3300pf (note 5) 45 ns bg1, bg2 t f bg fall time c load = 3300pf (note 5) 55 ns tg1/bg1 t 1d tg1 off to bg1 on delay, switch c on delay c load = 3300pf each driver 80 ns bg1/tg1 t 2d bg1 off to tg1 on delay, synchronous switch d on delay c load = 3300pf each driver 80 ns tg2/bg2 t 3d tg2 off to bg2 on delay, synchronous switch b on delay c load = 3300pf each driver 80 ns bg2/tg2 t 4d bg2 off to tg2 on delay, switch a on delay c load = 3300pf each driver 80 ns mode transition 1 bg1 off to bg2 on delay, switch a on delay c load = 3300pf each driver 250 ns mode transition 2 bg2 off to bg1 on delay, synchronous switch d on delay c load = 3300pf each driver 250 ns t on(min,boost) minimum on-time for main switch in boost operation switch c (note 6) 200 ns t on(min,buck) minimum on-time for synchronous switch in buck operation switch b (note 6) 180 ns internal v cc regulator v intvcc internal v cc voltage 7v < v in < 30v, v extvcc = 5v l 5.7 6 6.3 v ? v ldo(loadreg) internal v cc load regulation i cc = 0ma to 20ma, v extvcc = 5v 0.2 2 % v extvcc extv cc switchover voltage i cc = 20ma, v extvcc rising l 5.4 5.7 v ? v extvcc(hys) extv cc switchover hysteresis 300 mv ? v extvcc extv cc switch drop voltage i cc = 20ma, v extvcc = 6v 150 300 mv oscillator and phase-locked loop f nom nominal frequency v pllfltr = 1.2v 260 300 330 khz f low lowest frequency v pllfltr = 0v 170 200 220 khz f high highest frequency v pllfltr = 2.4v 340 400 440 khz r pllin pllin input resistance 50 k i plllpf phase detector output current f pllin < f osc f pllin > f osc (note 9) C15 15 a a
ltc3780 5 3780fe note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j for the qfn package is calculated from the temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 34c/w) note 3: the ic is tested in a feedback loop that servos v ith to a speci? ed voltage and measures the resultant v osense . note 4: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 5: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 6: the minimum on-time condition is speci? ed for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 7: the ltc3780e is guaranteed to meet performance speci? cations from 0c to 85c. performance over the C40c to 85c operating junction temperature range is assured by design, characterization and correlation with statistical process controls. the ltc3780i is guaranteed over the C40c to 125c operating junction temperature range. the ltc3780mp is guaranteed and tested over the full C55 to 125c operating junction temperature range. note 8: this parameter is guaranteed by design. note 9: f osc is the running frequency for the application. symbol parameter conditions min typ max units pgood output ? v fbh pgood upper threshold v osense rising 5.5 7.5 10 % ? v fbl pgood lower threshold v osense falling C5.5 C7.5 C10 % ? v fb(hyst) pgood hysteresis v osense returning 2.5 % v pgl pgood low voltage i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 a electrical characteristics the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v in = 15v unless otherwise noted.
ltc3780 6 3780fe typical performance characteristics ef? ciency vs output current (boost operation) ef? ciency vs output current ef? ciency vs output current (buck operation) supply current vs input voltage internal 6v ldo line regulation extv cc voltage drop intv cc and extv cc switch voltage vs temperature extv cc switch resistance vs temperature load regulation t a = 25c, unless otherwise noted. i load (a) 0.01 40 efficiency (%) 80 90 100 0.1 1 10 3780 g01 70 60 50 burst dcm ccm v in = 6v v out = 12v i load (a) 0.01 40 efficiency (%) 80 90 100 0.1 1 10 3780 g02 70 60 50 burst dcm ccm v in = 12v v out = 12v i load (a) 0.01 40 efficiency (%) 80 90 100 0.1 1 10 3780 g03 70 60 50 sc dcm ccm v in = 18v v out = 12v input voltage (v) 05 0 supply current (a) 1000 2500 10 20 25 3780 g04 500 2000 1500 15 30 35 v fcb = 0v standby shutdown input voltage (v) 0 intv cc voltage (v) 5.5 6.0 6.5 15 25 3780 g05 5.0 4.5 510 20 30 35 4.0 3.5 current (ma) 0 0 extv cc voltage drop (mv) 20 40 60 80 100 120 10 20 30 40 3780 g06 50 temperature (c) C75 C50 5.55 intv cc and extv cc switch voltage (v) 5.60 5.70 5.75 5.80 6.05 5.90 0 50 75 3780 g07 5.65 5.95 6.00 5.85 C25 25 100 125 intv cc voltage extv cc switchover threshold temperature (c) C75 C50 C25 0 extv cc switch resistance () 2 5 0 50 75 3780 g08 1 4 3 25 100 125 load current (a) 0 normalized v out (%) C0.2 C0.1 0 4 3780 g09 C0.3 C0.4 C0.5 1 2 3 5 v in = 18v fcb = 0v v out = 12v v in = 12v v in = 6v
ltc3780 7 3780fe continuous current mode (ccm, v in = 6v, v out = 12v) continuous current mode (ccm, v in = 12v, v out = 12v) continuous current mode (ccm, v in = 18v, v out = 12v) burst mode operation (v in = 6v, v out = 12v) burst mode operation (v in = 12v, v out = 12v) skip-cycle mode (v in = 18v, v out = 12v) discontinuous current mode (dcm, v in = 6v, v out = 12v) discontinuous current mode (dcm, v in = 12v, v out = 12v) discontinuous current mode (dcm, v in = 18v, v out = 12v) typical performance characteristics sw2 10v/div sw1 10v/div v out 100mv/div 5s/div v in = 6v v out = 12v 3780 g10 i l 2a/div sw2 10v/div sw1 10v/div v out 100mv/div 5s/div v in = 12v v out = 12v 3780 g11 i l 2a/div sw2 10v/div sw1 10v/div v out 100mv/div 5s/div v in = 18v v out = 12v 3780 g12 i l 2a/div sw2 10v/div sw1 10v/div v out 500mv/div 25s/div v in = 6v v out = 12v 3780 g13 i l 2a/div sw2 10v/div sw1 10v/div v out 200mv/div 10s/div v in = 12v v out = 12v 3780 g14 i l 2a/div sw2 10v/div sw1 10v/div v out 100mv/div 2.5s/div v in = 18v v out = 12v 3780 g15 i l 1a/div sw2 10v/div sw1 10v/div v out 100mv/div 5s/div v in = 6v v out = 12v 3780 g16 i l 1a/div sw2 10v/div sw1 10v/div v out 100mv/div 5s/div v in = 12v v out = 12v 3780 g17 i l 2a/div sw2 10v/div sw1 10v/div v out 100mv/div 2.5s/div v in = 18v v out = 12v 3780 g18 i l 1a/div t a = 25c, unless otherwise noted.
ltc3780 8 3780fe oscillator frequency vs temperature undervoltage reset vs temperature minimum current sense threshold vs duty factor (buck) maximum current sense threshold vs duty factor (boost) maximum current sense threshold vs duty factor (buck) minimum current sense threshold vs temperature peak current threshold vs v ith (boost) valley current threshold vs v ith (buck) current foldback limit typical performance characteristics temperature (c) C75 C50 0 frequency (khz) 50 150 200 250 50 450 3780 g19 100 0 C25 75 100 25 125 300 350 400 v pllfltr = 2.4v v pllfltr = 1.2v v pllfltr = 0v temperature (c) C75 C50 C25 3.0 undervoltage reset (v) 3.4 4.2 4.0 0 50 75 3780 g20 3.2 3.8 3.6 25 100 125 duty factor (%) C80 i sense + (mv) C60 C40 C20 80 60 40 20 3780 g21 0 100 duty factor (%) 0 i sense + (mv) 140 160 80 3780 g22 120 100 20 40 60 100 180 duty factor (%) 110 i snese + (mv) 120 130 140 20 40 60 80 3780 g23 100 0 temperature (c) C75 C50 50 100 200 25 75 3780 g24 0 C50 C25 0 50 100 125 C100 C150 150 maximum i snese + threshold (mv) boost buck v ith (v) 0 C100 i sense + (mv) C50 0 50 100 200 0.4 0.8 1.2 1.6 3780 g25 1.8 2.4 150 v ith (v) 0 C150 i sense + (mv) C100 C50 0 50 100 0.4 0.8 1.2 1.6 3780 g26 2.0 2.4 v osense (v) 0 0 i sense + (mv) 40 80 120 160 200 buck boost 0.2 0.4 0.6 3780 g32 0.8 t a = 25c, unless otherwise noted.
ltc3780 9 3780fe pin functions load step load step load step line transient line transient typical performance characteristics v out 500mv/div 200s/div v in = 18v v out = 12v load step: 0a to 5a continuous mode 3780 g27 i l 5a/div v out 500mv/div 200s/div v in = 12v v out = 12v load step: 0a to 5a continuous mode 3780 g28 i l 5a/div v out 500mv/div 200s/div v in = 6v v out = 12v load step: 0a to 5a continuous mode 3780 g29 i l 5a/div v out 500mv/div v in 10v/div 500s/div v out = 12v i load = 1a v in step: 7v to 20v continuous mode 3780 g30 i l 1a/div v out 500mv/div v in 10v/div 500s/div v out = 12v i load = 1a v in step: 20v to 7v continuous mode 3780 g31 i l 1a/div (ssop/qfn) pgood (pin 1/pin 30): open-drain logic output. pgood is pulled to ground when the output voltage is not within 7.5% of the regulation point. ss (pin 2/pin 31): soft-start reduces the input power sources surge currents by gradually increasing the controllers current limit. a minimum value of 6.8nf is recommended on this pin. sense + (pin 3/pin 1): the (+) input to the current sense and reverse current detect comparators. the i th pin voltage and built-in offsets between sense C and sense + pins, in conjunction with r sense , set the current trip threshold. sense C (pin 4/pin 2): the (C) input to the current sense and reverse current detect comparators. i th (pin 5/pin 3): current control threshold and error ampli? er compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v. t a = 25c, unless otherwise noted.
ltc3780 10 3780fe pin functions (ssop/qfn) v osense (pin 6/pin 4): error ampli? er feedback input. this pin connects the error ampli? er input to an external resistor divider from v out . sgnd (pin 7/pin 5): signal ground. all small-signal com- ponents and compensation components should connect to this ground, which should be connected to pgnd at a single point. run (pin 8/pin 6): run control input. forcing the run pin below 1.5v causes the ic to shut down the switching regulator circuitry. there is a 100k resistor between the run pin and sgnd in the ic. do not apply >6v to this pin. fcb (pin 9/pin 7): forced continuous control input. the voltage applied to this pin sets the operating mode of the controller. when the applied voltage is less than 0.8v, the forced continuous current mode is active. when this pin is allowed to ? oat, the burst mode operation is active in boost operation and the skip-cycle mode is active in buck operation. when the pin is tied to intv cc , the constant frequency discontinuous current mode is active in buck or boost operation. pllfltr (pin 10/pin 8): the phase-locked loops lowpass ? lter is tied to this pin. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. pllin (pin 11/pin 10): external synchronization input to phase detector. this pin is internally terminated to sgnd with 50k. the phase-locked loop will force the rising bottom gate signal of the controller to be synchronized with the rising edge of the pllin signal. stbymd (pin 12/pin 11): ldo control pin. determines whether the internal ldo remains active when the control- ler is shut down. see operation section for details. if the stbymd pin is pulled to ground, the ss pin is internally pulled to ground, preventing start-up and thereby provid- ing a single control pin for turning off the controller. to keep the ldo active when run is low, for example to power a wake up circuit which controls the state of the run pin, bypass stbymd to signal ground with a 0.1f capacitor, or use a resistor divider from v in to keep the pin within 2v to 5v. boost2, boost1 (pins 13, 24/pins 14, 27): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c a and c b (figure 11) connects here. the boost2 pin swings from a diode voltage below intv cc up to v in + intv cc . the boost1 pin swings from a diode voltage below intv cc up to v out + intv cc . tg2, tg1 (pins 14, 23/pins 15, 26): top gate drive. drives the top n-channel mosfet with a voltage swing equal to intv cc superimposed on the switch node voltage sw. sw2, sw1 (pins 15, 22/pins 17, 24): switch node. the (C) terminal of the bootstrap capacitor c a and c b (figure 11) connects here. the sw2 pin swings from a schottky diode (external) voltage drop below ground up to v in . the sw1 pin swings from a schottky diode (external) voltage drop below ground up to v out . bg2, bg1 (pins 16, 18/pins 18, 20): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and intv cc . pgnd (pin 17/pin 19): power ground. connect this pin closely to the source of the bottom n-channel mosfet, the (C) terminal of c vcc and the (C) terminal of c in (figure 11). intv cc (pin 19/pin 21): internal 6v regulator output. the driver and control circuits are powered from this voltage. bypass this pin to ground with a minimum of 4.7f low esr tantalum or ceramic capacitor. extv cc (pin 20/pin 22): external v cc input. when extv cc exceeds 5.7v, an internal switch connects this pin to intv cc and shuts down the internal regulator so that the controller and gate drive power is drawn from extv cc . do not exceed 7v at this pin and ensure that extv cc < v in . v in (pin 21/pin 23): main input supply. bypass this pin to sgnd with an rc ? lter (1, 0.1f). exposed pad (pin 33, qfn only): this pin is sgnd and must be soldered to pcb ground.
ltc3780 11 3780fe block diagram C + C + boost2 intv cc v in tg2 bg2 bg1 r sense pgnd fcb fcb intv cc intv cc intv cc i lim sw2 sw1 tg1 boost1 v osense i th v fb 0.86v v out 0.80v 3780 bd ov ea shdn rst 4(v fb ) run/ ss buck logic boost logic sense + sense C C + i rev C + i cmp slope 1.2v 4(v fb ) ss 1.2a 100k run fcb stbymd C + 5.7v 6v v in v in v ref internal supply extv cc intv cc sgnd + 6v ldo reg C + C + C + clk 0.86v 0.74v v osense r lp c lp oscillator phase det pllfltr pllin 50k f in pgood
ltc3780 12 3780fe operation main control loop the ltc3780 is a current mode controller that provides an output voltage above, equal to or below the input voltage. the ltc proprietary topology and control architecture em- ploys a current-sensing resistor in buck or boost modes. the sensed inductor current is controlled by the voltage on the i th pin, which is the output of the ampli? er ea. the v osense pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. the top mosfet drivers are biased from ? oating boost- strap capacitors c a and c b (figure 11), which are normally recharged through an external diode when the top mosfet is turned off. schottky diodes across the synchronous switch d and synchronous switch b are not required, but provide a lower drop during the dead time. the addition of the schottky diodes will typically improve peak ef? ciency by 1% to 2% at 400khz. the main control loop is shut down by pulling the run pin low. when the run pin voltage is higher than 1.5v, an internal 1.2a current source charges soft-start capacitor c ss at the ss pin. the i th voltage is then clamped to the ss voltage while c ss is slowly charged during start-up. this soft-start clamping prevents abrupt current from being drawn from the input power supply. power switch control figure 1 shows a simpli? ed diagram of how the four power switches are connected to the inductor, v in , v out and gnd. figure 2 shows the regions of operation for the ltc3780 as a function of duty cycle d. the power switches are properly controlled so the transfer between modes is continuous. when v in approaches v out , the buck-boost region is reached; the mode-to-mode transition time is typically 200ns. buck region (v in > v out ) switch d is always on and switch c is always off during this mode. at the start of every cycle, synchronous switch b is turned on ? rst. inductor current is sensed when synchronous switch b is turned on. after the sensed in- ductor current falls below the reference voltage, which is proportional to v ith , synchronous switch b is turned off and switch a is turned on for the remainder of the cycle. switches a and b will alternate, behaving like a typical synchronous buck regulator. the duty cycle of switch a increases until the maximum duty cycle of the converter in buck mode reaches d max_buck , given by: d max_buck = 100% C d buck-boost where d buck-boost = duty cycle of the buck-boost switch range: d buck-boost = (200ns ? f) ? 100% and f is the operating frequency in hz. figure 3 shows typical buck mode waveforms. if v in approaches v out , the buck-boost region is reached. buck-boost (v in ? v out ) when v in is close to v out , the controller is in buck-boost mode. figure 4 shows typical waveforms in this mode. every cycle, if the controller starts with switches b and d turned on, switches a and c are then turned on. finally, switches a and d are turned on for the remainder of the time. if the controller starts with switches a and c turned tg2 bg2 tg1 bg1 r sense 3780 f01 a b d c l sw2 sw1 v in v out a on, b off pwm c, d switches d on, c off pwm a, b switches four switch pwm 98% d max boost 3% d min buck d min boost d max buck boost region buck region buck/boost region 3780 f02 figure 1. simpli? ed diagram of the output switches figure 2. operating mode vs duty cycle
ltc3780 13 3780fe operation on, switches b and d are then turned on. finally, switches a and d are turned on for the remainder of the time. boost region (v in < v out ) switch a is always on and synchronous switch b is always off in boost mode. every cycle, switch c is turned on ? rst. inductor current is sensed when synchronous switch c is turned on. after the sensed inductor current exceeds the reference voltage which is proportional to v ith , switch c is turned off and synchronous switch d is turned on for switch a clock switch b switch c switch d i l 0v high 3780 f03 figure 3. buck mode (v in > v out ) switch a clock switch b switch c switch d i l 3780 f04a (4a) buck-boost mode (v in v out ) switch a clock switch b switch c switch d i l 3780 f04b (4b) buck-boost mode (v in v out ) figure 4. buck-boost mode the remainder of the cycle. switches c and d will alternate, behaving like a typical synchronous boost regulator. the duty cycle of switch c decreases until the minimum duty cycle of the converter in boost mode reaches d min_boost , given by: d min_boost = d buck-boost where d buck-boost is the duty cycle of the buck-boost switch range: d buck-boost = (200ns ? f) ? 100% and f is the operating frequency in hz. figure 5 shows typical boost mode waveforms. if v in ap- proaches v out , the buck-boost region is reached. switch a clock switch b switch c switch d i l 0v high 3780 f05 figure 5. boost mode (v in < v out ) low current operation the fcb pin is used to select among three modes for both buck and boost operations by accepting a logic input. figure 6 shows the different modes. fcb pin buck mode boost mode 0v to 0.75v force continuous mode force continuous mode 0.85v to 5v skip-cycle mode burst mode operation >5.3v dcm with constant freq dcm with constant freq figure 6. different operating modes when the fcb pin voltage is lower than 0.8v, the controller behaves as a continuous, pwm current mode synchronous switching regulator. in boost mode, switch a is always on. switch c and synchronous switch d are alternately turned on to maintain the output voltage independent of direction of inductor current. every ten cycles, switch a is forced off for about 300ns to allow boost capacitor c a (figure 13) to recharge. in buck mode, synchronous switch d is always
ltc3780 14 3780fe operation on. switch a and synchronous switch b are alternately turned on to maintain the output voltage independent of direction of inductor current. every ten cycles, synchro- nous switch d is forced off for about 300ns to allow c b to recharge. this is the least ef? cient operating mode at light load, but may be desirable in certain applications. in this mode, the output can source or sink current. when the fcb pin voltage is below v intvcc C 1v, but greater than 0.8v, the controller enters burst mode operation in boost operation or enters skip-cycle mode in buck opera- tion. during boost operation, burst mode operation sets a minimum output current level before inhibiting the switch c and turns off synchronous switch d when the inductor current goes negative. this combination of requirements will, at low currents, force the i th pin below a voltage threshold that will temporarily inhibit turn-on of power switches c and d until the output voltage drops. there is 100mv of hysteresis in the burst comparator tied to the i th pin. this hysteresis produces output signals to the mosfets c and d that turn them on for several cycles, followed by a variable sleep interval depending upon the load current. the maximum output voltage ripple is limited to 3% of the nominal dc output voltage as determined by a resistive feedback divider. during buck operation at no load, switch a is turned on for its minimum on-time. this will not occur every clock cycle when the output load current drops below 1% of the maximum designed load. the body diode of synchronous switch b or the schottky diode, which is in parallel with switch b, is used to dis- charge the inductor current; switch b only turns on every ten clock cycles to allow c b to recharge. as load current is applied, switch a turns on every cycle, and its on-time begins to increase. at higher current, switch b turns on brie? y after each turn-off of switch a. switches c and d remain off at light load, except to refresh ca (figure 11) every 10 clock cycles. in burst mode operation/skip-cycle mode, the output is prevented from sinking current. when the fcb pin voltage is tied to the intv cc pin, the controller enters constant frequency discontinuous current mode (dcm). for boost operation, synchronous switch d is held off whenever the i th pin is below a threshold volt- age. in every cycle, switch c is used to charge inductor current. after the output voltage is high enough, the controller will enter continuous current buck mode for one cycle to discharge inductor current. in the following cycle, the controller will resume dcm boost operation. for buck operation, constant frequency discontinuous current mode sets a minimum negative inductor current level. synchronous switch b is turned off whenever inductor current is lower than this level. at very light loads, this constant frequency operation is not as ef? cient as burst mode operation or skip-cycle, but does provide lower noise, constant frequency operation. frequency synchronization and frequency setup the phase-locked loop allows the internal oscillator to be synchronized to an external source via the pllin pin. the phase detector output at the pllfltr pin is also the dc frequency control input of the oscillator. the frequency ranges from 200khz to 400khz, corresponding to a dc voltage input from 0v to 2.4v at pllfltr. when locked, the pll aligns the turn on of the top mosfet to the ris- ing edge of the synchronizing signal. when pllin is left open, the pllfltr pin goes low, forcing the oscillator to its minimum frequency. intv cc /extv cc power power for all power mosfet drivers and most inter- nal circuitry is derived from the intv cc pin. when the extv cc pin is left open, an internal 6v low dropout linear regulator supplies intv cc power. if extv cc is taken above 5.7v, the 6v regulator is turned off and an internal switch is turned on, connecting extv cc to intv cc . this allows the intv cc power to be derived from a high ef? ciency external source. power good (pgood) pin the pgood pin is connected to an open drain of an internal mosfet. the mosfet turns on and pulls the pin low when the output is not within 7.5% of the nominal output level as determined by the resistive feedback divider. when the output meets the 7.5% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 7v.
ltc3780 15 3780fe operation foldback current foldback current limiting is activated when the output voltage falls below 70% of its nominal level, reducing power waste. during start-up, foldback current limiting is disabled. input undervoltage reset the ss capacitor will be reset if the input voltage is al- lowed to fall below approximately 4v. the ss capacitor will attempt to charge through a normal soft-start ramp after the input voltage rises above 4v. output overvoltage protection an overvoltage comparator guards against transient over- shoots (>7.5%) as well as other more serious conditions that may overvoltage the output. in this case, synchronous switch b and synchronous switch d are turned on until the overvoltage condition is cleared or the maximum negative current limit is reached. when inductor current is lower than the maximum negative current limit, synchronous switch b and synchronous switch d are turned off, and switch a and switch c are turned on until the inductor current reaches another negative current limit. if the comparator still detects an overvoltage condition, switch a and switch c are turned off, and synchronous switch b and synchronous switch d are turned on again. short-circuit protection and current limit switch a on-time is limited by output voltage. when output voltage is reduced and is lower than its nominal level, switch a on-time will be reduced. in every boost mode cycle, current is limited by a voltage reference, which is proportional to the i th pin voltage. the maximum sensed current is limited to 160mv. in every buck mode cycle, the maximum sensed current is limited to 130mv. standby mode pin the stbymd pin is a three-state input that controls circuitry within the ic as follows: when the stbymd pin is held at ground, the ss pin is pulled to ground. when the pin is left open, the internal ss current source charges the ss capacitor, allowing turn-on of the controller and activat- ing necessary internal biasing. when the stbymd pin is taken above 2v, the internal linear regulator is turned on independent of the state on the run and ss pins, providing an output power source for wake-up circuitry. bypass the pin with a small capacitor (0.1f) to ground if the pin is not connected to a dc potential.
ltc3780 16 3780fe applications information figure 11 is a basic ltc3780 application circuit. external component selection is driven by the load requirement, and begins with the selection of r sense and the inductor value. next, the power mosfets are selected. finally, c in and c out are selected. this circuit can be con? gured for operation up to an input voltage of 36v. selection of operation frequency the ltc3780 uses a constant frequency architecture and has an internal voltage controlled oscillator. the switching frequency is determined by the internal oscillator capacitor. this internal capacitor is charged by a ? xed current plus an additional current that is proportional to the voltage applied to the pllfltr pin. the frequency of this oscillator can be varied over a 2-to-1 range. the pllfltr pin can be grounded to lower the frequency to 200khz or tied to 2.4v to yield approximately 400khz. when pllin is left open, the pllfltr pin goes low, forcing the oscillator to minimum frequency. a graph for the voltage applied to the pllfltr pin vs frequency is given in figure 7. as the operating frequency is increased the gate charge losses will be higher, reducing ef? ciency. the maximum switching frequency is approxi- mately 400khz. inductor selection the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. the inductor value has a direct effect on ripple current. the inductor current ripple ? i l is typically set to 20% to 40% of the maximum inductor current at boost mode v in(min) . for a given ripple the inductance terms in continuous mode are as follows: l vvv i boost in min out in min out > () () () ( to t t 2 100 ? m max out buck out in max o ripple v h l vv v ) () t t , to 2 > u ut out max in max i ripple v h () t ttt () () 100 ? where: f is operating frequency, hz % ripple is allowable inductor current ripple, % v in(min) is minimum input voltage, v v in(max) is maximum input voltage, v v out is output voltage, v i out(max) is maximum output load current for high ef? ciency, choose an inductor with low core loss, such as ferrite and molypermalloy (from magnetics, inc.). also, the inductor should have low dc resistance to reduce the i 2 r losses, and must be able to handle the peak inductor current without saturating. to minimize radiated noise, use a toroid, pot core or shielded bobbin inductor. r sense selection and maximum output current r sense is chosen based on the required output current. the current comparator threshold sets the peak of the inductor current in boost mode and the maximum inductor valley current in buck mode. in boost mode, the maximum average load current at v in(min) is: i mv r i v out max boost sense l in (, ) ( ns = ? ? ? ? ? ? 160 2 m min out v ) pllfltr pin voltage (v) 0 0 operating frequency (khz) 50 150 200 250 1 2 2.5 450 3780 f07 100 0.5 1.5 300 350 400 figure 7. frequency vs pllfltr pin voltage
ltc3780 17 3780fe applications information where ? i l is peak-to-peak inductor ripple current. in buck mode, the maximum average load current is: i out(max,buck) = 130mv r sense + i l 2 figure 8 shows how the load current (i maxload ? r sense ) varies with input and output voltage the maximum current sensing r sense value for the boost mode is: r sense(max) = 2 s 160mv s v in(min) 2 s i out(max,boost) s v out + i l,boost s v in(min) the maximum current sensing r sense value for the buck mode is: r sense(max) = 2 s 130mv 2 s i out(max,buck) C i l,buck the ? nal r sense value should be lower than the calculated r sense(max) in both the boost and buck modes. a 20% to 30% margin is usually recommended. c in and c out selection in boost mode, input current is continuous. in buck mode, input current is discontinuous. in buck mode, the selection of input capacitor c in is driven by the need to ? lter the input square wave current. use a low esr capacitor sized to handle the maximum rms current. for buck operation, the input rms current is given by: i rms i out(max) ? v out v in ? v in v out C1 this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that ripple cur- rent ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. in boost mode, the discontinuous current shifts from the input to the output, so c out must be capable of reducing the output voltage ripple. the effects of esr (equivalent series resistance) and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. the steady ripple due to charging and discharging the bulk capacitance is given by: ripple (boost,cap) = i out(max) ?v out ?v in(min) ( ) c out ?v out ?f v ripple (buck,cap) = i out(max) ?v in(max ) ?v out ( ) c out ?v in(max) ?f v where c out is the output ? lter capacitor. the steady ripple due to the voltage drop across the esr is given by: ? v boost,esr = i l(max,boost) ? esr ? v buck,esr = i l(max,buck) ? esr multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. ceramic capacitors have excellent low esr characteristics but can have a high voltage coef? cient. capacitors are now available with low esr and high ripple current ratings, such as os-con and poscap . v in /v out (v) 0.1 100 i max(load) ? r sense (mv) 110 120 130 140 160 110 3780 f08 150 figure 8. load current vs v in /v out
ltc3780 18 3780fe applications information power mosfet selection and ef? ciency considerations the ltc3780 requires four external n-channel power mosfets, two for the top switches (switch a and d, shown in figure 1) and two for the bottom switches (switch b and c shown in figure 1). important parameters for the power mosfets are the breakdown voltage v br,dss , threshold voltage v gs,th , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the drive voltage is set by the 6v intv cc supply. con- sequently, logic-level threshold mosfets must be used in ltc3780 applications. if the input voltage is expected to drop below 5v, then the sub-logic threshold mosfets should be considered. in order to select the power mosfets, the power dis- sipated by the device must be known. for switch a, the maximum power dissipation happens in boost mode, when it remains on all the time. its maximum power dissipation at maximum output current is given by: p v v ir a boost out in out max t ds on ,()() sss = ? ? ? ? ? ? 2 where t is a normalization factor (unity at 25c) ac- counting for the signi? cant variation in on-resistance with temperature, typically about 0.4%/c as shown in figure 9. for a maximum junction temperature of 125c, using a value t = 1.5 is reasonable. switch b operates in buck mode as the synchronous recti? er. its power dissipation at maximum output current is given by: p vv v ir bbuck in out in out max t ds on ,()() C sss = 2 switch c operates in boost mode as the control switch. its power dissipation at maximum current is given by: p vvv v ir kv i v cf c boost out in out in out max t ds on out out max in rss ,()() () C sss ss ss = () + 2 2 3 where c rss is usually speci? ed by the mosfet manufactur- ers. the constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. for switch d, the maximum power dissipation happens in boost mode, when its duty cycle is higher than 50%. its maximum power dissipation at maximum output current is given by: p v v v v i d boost in out out in out max ,() ss s = ? ? ? ? ? ? 2 t tdson r s () for the same output voltage and current, switch a has the highest power dissipation and switch b has the lowest power dissipation unless a short occurs at the output. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p ? r th(ja) the r th(ja) to be used in the equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(jc) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. junction temperature (c) C50 r t normalized on-resistance () 1.0 1.5 150 3780 f09 0.5 0 0 50 100 2.0 figure 9. normalized r ds(on) vs temperature
ltc3780 19 3780fe applications information schottky diode (d1, d2) selection and light load operation the schottky diodes d1 and d2 shown in figure 1 conduct during the dead time between the conduction of the power mosfet switches. they are intended to prevent the body diode of synchronous switches b and d from turning on and storing charge during the dead time. in particular, d2 signi? cantly reduces reverse recovery current between switch d turn-off and switch c turn-on, which improves converter ef? ciency and reduces switch c voltage stress. in order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. in buck mode, when the fcb pin voltage is 0.85 < v fcb < 5v, the converter operates in skip-cycle mode. in this mode, synchronous switch b remains off until the induc- tor peak current exceeds one-? fth of its maximum peak current. as a result, d1 should be rated for about one-half to one-third of the full load current. in boost mode, when the fcb pin voltage is higher than 5.3v, the converter operates in discontinuous current mode. in this mode, synchronous switch d remains off until the inductor peak current exceeds one-? fth of its maximum peak current. as a result, d2 should be rated for about one-third to one-fourth of the full load current. in buck mode, when the fcb pin voltage is higher than 5.3v, the converter operates in constant frequency discontinu- ous current mode. in this mode, synchronous switch b remains on until the inductor valley current is lower than the sense voltage representing the minimum negative inductor current level (v sense = C5mv). both switch a and b are off until next clock signal. in boost mode, when the fcb pin voltage is 0.85 < v fcb < 5.3v, the converter operates in burst mode operation. in this mode, the controller clamps the peak inductor current to approximately 20% of the maximum inductor current. the output voltage ripple can increase during burst mode operation. intv cc regulator an internal p-channel low dropout regulator produces 6v at the intv cc pin from the v in supply pin. intv cc powers the drivers and internal circuitry within the ltc3780. the intv cc pin regulator can supply a peak current of 40ma and must be bypassed to ground with a minimum of 4.7f tantalum, 10f special polymer or low esr type electrolytic capacitor. a 1f ceramic capacitor placed directly adjacent to the intv cc and pgnd ic pins is highly recommended. good bypassing is necessary to supply the high transient current required by mosfet gate drivers. higher input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi- mum junction temperature rating for the ltc3780 to be exceeded. the system supply current is normally dominated by the gate charge current. additional external loading of the intv cc also needs to be taken into account for the power dissipation calculations. the total intv cc current can be supplied by either the 6v internal linear regulator or by the extv cc input pin. when the voltage applied to the extv cc pin is less than 5.7v, all of the intv cc current is supplied by the internal 6v linear regulator. power dis- sipation for the ic in this case is v in ? i intvcc , and overall ef? ciency is lowered. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, a typical application operating in continuous current mode might draw 24ma from a 24v supply when not using the extv cc pin: t j = 70c + 24ma ? 24v ? 34c/w = 90c use of the extv cc input pin reduces the junction tem- perature to: t j = 70c + 24ma ? 6v ? 34c/w = 75c to prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum v in .
ltc3780 20 3780fe applications information extv cc connection the ltc3780 contains an internal p-channel mosfet switch connected between the extv cc and intv cc pins. when the voltage applied to extv cc rises above 5.7v, the internal regulator is turned off and a switch connects the extv cc pin to the intv cc pin thereby supplying internal power. the switch remains closed as long as the voltage applied to extv cc remains above 5.5v. this allows the mosfet driver and control power to be derived from the output when (5.7v < v out < 7v) and from the internal regulator when the output is out of regulation (start-up, short-circuit). if more current is required through the extv cc switch than is speci? ed, an external schottky diode can be interposed between the extv cc and intv cc pins. ensure that extv cc v in . the following list summarizes the three possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 6v regulator at the cost of a small ef? ciency penalty. 2. extv cc connected directly to v out (5.7v < v out < 7v). this is the normal connection for a 6v regulator and provides the highest ef? ciency. 3. extv cc connected to an external supply. if an external supply is available in the 5.5v to 7v range, it may be used to power extv cc provided it is compatible with the mosfet gate drive requirements. output voltage the ltc3780 output voltage is set by an external feedback resistive divider carefully placed across the output capacitor. the resultant feedback signal is compared with the internal precision 0.800v voltage reference by the error ampli? er. the output voltage is given by the equation: vv r r out =+ ? ? ? ? ? ? 08 1 2 1 s topside mosfet driver supply (c a , d a , c b , d b ) referring to figure 11, the external bootstrap capacitors c a and c b connected to the boost1 and boost2 pins supply the gate drive voltage for the topside mosfet switches a and d. when the top mosfet switch a turns on, the switch node sw2 rises to v in and the boost2 pin rises to approximately v in + intv cc . when the bottom mosfet switch b turns on, the switch node sw2 drops to low and the boost capacitor c b is charged through d b from intv cc . when the top mosfet switch d turns on, the switch node sw1 rises to v out and the boost1 pin rises to approximately v out + intv cc . when the bottom mosfet switch c turns on, the switch node sw1 drops to low and the boost capacitor c a is charged through d a from intv cc . the boost capacitors c a and c b need to store about 100 times the gate charge required by the top mosfet switch a and d. in most applications a 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. run function the run pin provides simple on/off control for the ltc3780. driving the run pin above 1.5v permits the controller to start operating. pulling run below 1.5v puts the ltc3780 into low current shutdown. do not apply more than 6v to the run pin. soft-start function soft-start reduces the input power sources surge cur- rents by gradually increasing the controllers current limit (proportional to an internally buffered and clamped equivalent of v ith ). an internal 1.2a current source charges up the c ss capacitor. as the voltage on ss increases from 0v to 2.4v, the internal current limit rises from 0v/r sense to 150mv/r sense . the output current limit ramps up slowly, taking 1.5s/f to reach full current. the output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. t irmp = 2.4v 1.2a ?c ss = 1.5s/f ( ) ?c ss do not apply more than 6v to the ss pin. current foldback is disabled during soft-start until the voltage on c ss reaches 2v. make sure c ss is large enough when there is loading during start-up.
ltc3780 21 3780fe applications information the standby mode (stbymd) pin function the standby mode (stbymd) pin provides several choices for start-up and standby operational modes. if the pin is pulled to ground, the ss pin is internally pulled to ground, preventing start-up and thereby providing a single control pin for turning off the controller. if the pin is left open or bypassed to ground with a capacitor, the ss pin is internally provided with a starting current, permitting external control for turning on the controller. if the pin is connected to a voltage greater than 1.25v, the internal regulator (intv cc ) will be on even when the controller is shut down (run pin voltage < 1.5v). in this mode, the onboard 6v linear regulator can provide power to keep-alive functions such as a keyboard controller. fault conditions: current limit and current foldback the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in boost mode, maximum sense voltage and the sense resistance determines the maximum allowed inductor peak current, which is: i l(max,boost) = 160mv r sense in buck mode, maximum sense voltage and the sense resistance determines the maximum allowed inductor valley current, which is: i l(max,buck) = 130mv r sense to further limit current in the event of a short circuit to ground, the ltc3780 includes foldback current limiting. if the output falls by more than 30%, then the maximum sense voltage is progressively lowered to about one third of its full value. fault conditions: overvoltage protection a comparator monitors the output for overvoltage con- ditions. the comparator (ov) detects overvoltage faults greater than 7.5% above the nominal output voltage. when the condition is sensed, switches a and c are turned off, and switches b and d are turned on until the overvoltage condition is cleared. during an overvoltage condition, a negative current limit (v sense = C60mv) is set to limit negative inductor current. when the sensed current inductor current is lower than C60mv, switch a and c are turned on, and switch b and d are turned off until the sensed current is higher than C20mv. if the output is still in overvoltage condition, switch a and c are turned off, and switch b and d are turned on again. ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. although all dissipative elements in circuit produce losses, four main sources account for most of the losses in ltc3780 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, sensing resistor, inductor and pc board traces and cause the ef? ciency to drop at high output currents. 2. transition loss. this loss arises from the brief amount of time switch a or switch c spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is signi? cant at input voltages above 20v and can be estimated from: transition loss 1.7a C1 ? v in2 ? i out ? c rss ? f where c rss is the reverse transfer capacitance.
ltc3780 22 3780fe applications information 3. intv cc current. this is the sum of the mosfet driver and control currents. this loss can be reduced by sup- plying intv cc current through the extv cc pin from a high ef? ciency source, such as an output derived boost network or alternate supply if available. 4. c in and c out loss. the input capacitor has the dif? cult job of ? ltering the large rms input current to the regula- tor in buck mode. the output capacitor has the more dif? cult job of ? ltering the large rms output current in boost mode. both c in and c out are required to have low esr to minimize the ac i 2 r loss and suf? cient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. 5. other losses. schottky diode d1 and d2 are respon- sible for conduction losses during dead time and light load conduction periods. inductor core loss occurs predominately at light loads. switch c causes reverse recovery current loss in boost mode. when making adjustments to improve ef? ciency, the input current is the best indicator of changes in ef? ciency. if you make a change and the input current decreases, then the ef? ciency has increased. if there is no change in input current, then there is no change in ef? ciency. design example as a design example, assume v in = 5v to 18v (12v nominal), v out = 12v (5%), i out(max) = 5a and f = 400khz. set the pllfltr pin at 2.4v for 400khz operation. the inductance value is chosen ? rst based on a 30% ripple current assumption. in buck mode, the ripple current is: = ? ? ? ? ? ? i v fl v v lbuck out out in , s sn 1 i ripple,buck = i l,buck s 100 i out % the highest value of ripple current occurs at the maximum input voltage. in boost mode, the ripple current is: = ? ? ? ? ? ? i v fl v v l boost in in out , s sn 1 i ripple,boost = i l,boost s 100 i in % the highest value of ripple current occurs at v in = v out /2. a 6.8h inductor will produce 11% ripple in boost mode (v in = 6v) and 29% ripple in buck mode (v in = 18v). the r sense resistor value can be calculated by using the maximum current sense voltage speci? cation with some accommodation for tolerances. r sense = 2 s 160mv s v in(min) 2 s i out(max,boost) s v out + i l,boost s v in(min) select an r sense of 10m. output voltage is 12v. select r1 as 20k. r2 is: r2 = v out ?r1 0.8 ?r1 select r2 as 280k. both r1 and r2 should have a toler- ance of no more than 1%. next, choose the mosfet switches. a suitable choice is the siliconix si4840 (r ds(on) = 0.009 (at v gs = 6v), c rss = 150pf, ja = 40c/w). the maximum power dissipation of switch a occurs in boost mode when switch a stays on all the time. assum- ing a junction temperature of t j = 150c with 150c = 1.5, the power dissipation at v in = 5v is: pw a boost , sss .. = ? ? ? ? ? ? = 12 5 5 1 5 0 009 1 94 2
ltc3780 23 3780fe applications information double-check the t j in the mosfet with 70c ambient temperature: t j = 70c + 1.94w ? 40c/w = 147.6c the maximum power dissipation of switch b occurs in buck mode. assuming a junction temperature of t j = 80c with 80c = 1.2, the power dissipation at v in = 18v is: p b,buck = 18 ? 12 18 ?5 2 ?1.2 ? 0.009 = 90mw double-check the t j in the mosfet at 70c ambient temperature: t j = 70c + 0.09w ? 40c/w = 73.6c the maximum power dissipation of switch c occurs in boost mode. assuming a junction temperature of t j = 110c with 110c = 1.4, the power dissipation at v in = 5v is: p c,boost = 12 ? 5 ( ) ?12 5 2 ?5 2 ?1.4 ? 0.009 + 2?12 3 ? 5 5 ?150p ? 400k = 1.27w double-check the t j in the mosfet at 70c ambient temperature: t j = 70c + 1.08w ? 40c/w = 113c the maximum power dissipation of switch d occurs in boost mode when its duty cycle is higher than 50%. assuming a junction temperature of t j = 100c with 100c = 1.35, the power dissipation at v in = 5v is: pw d boost , ssss = ? ? ? ? ? ? = 5 12 12 5 5 1 35 0 009 0 73 2 double-check the t j in the mosfet at 70c ambient temperature: t j = 70c + 0.73w ? 40c/w = 99c c in is chosen to ? lter the square current in buck mode. in this mode, the maximum input current peak is: ia in peak max buck ,(, ) s % . =+ ? ? ? ? ? ? = 51 29 2 57 a low esr (10m) capacitor is selected. input voltage ripple is 57mv (assuming esr dominate ripple). c out is chosen to ? lter the square current in boost mode. in this mode, the maximum output current peak is: i out peak max boost ,(, ) ss % . =+ ? ? ? ? ? ? = 12 5 51 11 2 10 6 6a a low esr (5m) capacitor is suggested. this capacitor will limit output voltage ripple to 53mv (assuming esr dominate ripple). pc board layout checklist the basic pc board layout requires a dedicated ground plane layer. also, for high current, a multilayer board provides heat sinking for power components. ? the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , switch a, switch b and d1 in one com- pact area. place c out , switch c, switch d and d2 in one compact area. one layout example is shown in figure 10. gnd v out c out l r sense 3780 f10 qd qc qb qa sw2 sw1 d1 d2 v in c in ltc3780 ckt figure 10. switches layout
ltc3780 24 3780fe applications information ? use immediate vias to connect the components (in- cluding the ltc3780s sgnd and pgnd pins) to the ground plane. use several large vias for each power component. ? use planes for v in and v out to maintain good voltage ? ltering and to keep power losses low. ? flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. connect the copper areas to any dc net (v in or gnd). ? segregate the signal and power grounds. all small- signal components should return to the sgnd pin at one point, which is then tied to the pgnd pin close to the sources of switch b and switch c. ? place switch b and switch c as close to the controller as possible, keeping the pgnd, bg and sw traces short. ? keep the high dv/dt sw1, sw2, boost1, boost2, tg1 and tg2 nodes away from sensitive small-signal nodes. ? the path formed by switch a, switch b, d1 and the c in capacitor should have short leads and pc trace lengths. the path formed by switch c, switch d, d2 and the c out capacitor also should have short leads and pc trace lengths. ? the output capacitor (C) terminals should be connected as close as possible the (C) terminals of the input capacitor. ? connect the top driver boost capacitor c a closely to the boost1 and sw1 pins. connect the top driver boost capacitor c b closely to the boost2 and sw2 pins. ? connect the input capacitors c in and output capacitors c out closely to the power mosfets. these capaci- tors carry the mosfet ac current in boost and buck mode. ? connect v osense pin resistive dividers to the (+) termi- nals of c out and signal ground. a small v osense bypass capacitor may be connected closely to the ltc3780 sgnd pin. the r2 connection should not be along the high current or noise paths, such as the input capacitors. ? route sense C and sense + leads together with minimum pc trace spacing. avoid sense lines pass through noisy area, such as switch nodes. the ? lter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. one layout example is shown in figure 12. ? connect the i th pin compensation network close to the ic, between i th and the signal ground pins. the capaci- tor helps to ? lter the effects of pcb noise and output voltage ripple voltage from the compensation loop. ? connect the intv cc bypass capacitor, c vcc , close to the ic, between the intv cc and the power ground pins. this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially.
ltc3780 25 3780fe applications information ltc3780 d a c f c out v out v in f in c c1 c c2 c ss c in 3780 f11 c a v pullup c b b d c l d1 a c vcc r sense d b r in pgood ss sense + boost1 tg1 sw1 v in extv cc intv cc bg1 pgnd bg2 sw2 tg2 boost2 1 2 3 i th v osense sgnd run fcb pllfltr pllin stbymd 5 6 7 8 9 10 11 12 sense C 4 rr c 24 23 22 21 20 19 18 17 16 15 14 13 r1 r2 r c r pu d2 figure 11. ltc3780 layout diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 sgnd pgnd r sense c r r 3780 f12 figure 12. sense lines layout
ltc3780 26 3780fe package description g package 24-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g24 ssop 0204 0.09 C 0.25 (.0035 C .010) 0 o C 8 o 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 7.90 C 8.50* (.311 C .335) 21 22 18 17 16 15 14 13 19 20 23 24 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 p 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 p 0.12
ltc3780 27 3780fe information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 p 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 31 1 2 32 bottom viewexposed pad 3.50 ref (4-sides) 3.45 p 0.10 3.45 p 0.10 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 p 0.05 3.50 ref (4 sides) 4.10 p 0.05 5.50 p 0.05 0.25 p 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer r = 0.05 typ 3.45 p 0.05 3.45 p 0.05
ltc3780 28 3780fe linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0309 rev e ? printed in usa related parts typical application ltc3780 d a bo540w d b bo540w c f 0.1f c out 330f 16v v out 12v 5a v in 5v to 32v c c1 0.01f c c2 47pf c ss 0.022f c in 22f 35v 3780 ta02 c a 0.22f v pullup c b 0.22f b si7884dp c si7884dp d si7884dp l 4.7h d1 b340a d2 b320a a si7884dp c vcc 4.7f 9m 10 pgood ss sense + sense C i th v osense boost1 tg1 sw1 v in extv cc intv cc 1 2 3 4 5 6 24 23 22 21 20 19 sgnd run fcb pllfltr bg1 pgnd bg2 sw2 pllin stbymd tg2 boost2 7 8 9 10 18 17 16 15 11 12 14 13 100 100 r1 8.06k, 1% r2 113k, 1% on/off 10k 2v r c 100k r pu 68pf c stbymd 0.01f + + 22f 16v, x7r s 3 3.3f 50v, x5r s 3 figure 13. ltc3780 12v/5a, buck-boost regulator part number description comments ltc1871/ltc1871-1 LTC1871-7 sepic, boost, flyback controller no r sense ?, 2.5v v in 36v burst mode operation, msop-10 package ltc3443 1.2a i out , 600khz, synchronous buck-boost dc/dc converter v in : 2.4v to 5.5v, v out : 2.4v to 5.25v, i q = 28a, i sd < 1a, ms package ltc3444 500ma i out , 1.5mhz synchronous buck-boost dc/dc converter v in : 2.7v to 5.5v, v out : 0.5v to 5.25v, optimized for wcdma rf ampli? er bias ltc3531/ltc3531-3 ltc3531-3.3 200ma i out , synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 2v to 5v, i q = 35a, i sd < 1a, ms, dfn packages ltc3532 500ma i out , 2mhz, synchronous buck-boost dc/dc converter v in : 2.4v to 5.5v, v out : 2.4v to 5.25v, i q = 35a, i sd < 1a, ms, dfn packages ltc3533 2a wide input voltage synchronous buck-boost dc/dc converter v in : 1.8v to 5.5v, v out : 1.8v to 5.25v, i q = 40a, i sd < 1a, dfn package ltc3785/ltc3785-1 10v, high ef? ciency, synchronous, no r sense , buck-boost controller v in : 2.7v to 10v, v out : 2.7v to 10v, i q = 86ma, i sd < 15a, qfn-24 package ltc4444/ltc4444-5 high voltage synchronous n-channel mosfet driver v in up to 100v, used with the ltc3780 for higher v in applications ltm4605 5a to 12a buck-boost module? 4.5v v in 20v, 0.8v v out 16v, 15mm 15mm 2.8mm lga package ltm4607 5a to 12a buck-boost module 4.5v v in 36v, 0.8v v out 24v, 15mm 15mm 2.8mm lga package no r sense and module are trademarks of linear technology corporation

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